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X20C05 1 high speed autostore? novram 4k X20C05 512 x 8 features ? fast access time: 35ns, 45ns, 55ns ? high reliability endurance: 1,000,000 nonvolatile store operations retention: 100 years minimum ? power-on recall e 2 prom data automatically recalled into sram upon power-up ? autostore? novram user enabled option automatically stores sram data into the e 2 prom array when v cc low threshold is detected open drain autostore status output pin ? software data protection locks out inadvertent store operations ? low power cmos standby: 250 m a ? infinite e 2 prom array recall, and ram read and write cycles ? upward compatible with x20c16 (16k) pin configuration plastic cerdip 3827 fhd f02 ne nc 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 i/o 0 i/o 1 i/o 2 v 1 v cc we as a 8 nc nc oe nc ce i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 X20C05 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 lcc plcc a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 nc i/o 0 a 8 nc nc nc oe nc ce i/o 7 i/o 6 nc ne nc v cc we as i/o 1 i/o 2 v ss nc i/o 3 i/o 4 i/o 5 4321323130 14 15 16 17 18 19 20 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 X20C05 (top view) 3827 fhd f03 description the xicor X20C05 is a 512 x 8 novram featuring a high-speed static ram overlaid bit-for-bit with a non- volatile electrically erasable prom (e 2 prom). the X20C05 is fabricated with advanced cmos floating gate technology to achieve high speed with low power and wide power-supply margin. the X20C05 features the jedec approved pinout for byte-wide memories, compatible with industry standard rams, roms, eproms, and e 2 proms. the novram design allows data to be easily trans- ferred from ram to e 2 prom (store) and e 2 prom to ram (recall). the store operation is completed in 5ms or less and the recall operation is completed in 5 m s or less. xicor novrams are designed for unlimited write operations to ram, either from the host or recalls from e 2 prom, and a minimum 1,000,000 store operations to the e 2 prom. data retention is specified to be greater than 100 years. autostore? novram is a trademark of xicor, inc. ?xicor, inc. 1991 - 1997 patents pending characteristics subject to change without notice 3827-2.7 7/31/97 t4/c0/d0 sh a pplication n ote available an56
X20C05 2 pin descriptions addresses (a 0 Ca 8 ) the address inputs select an 8-bit memory location during a read or write operation. chip enable ( ce ) the chip enable input must be low to enable all read/ write operations. when ce is high, power consumption is reduced. output enable ( oe ) the output enable input controls the data output buffers and is used to initiate read and recall operations. output enable low disables a store operation regardless of the state of ce , we, or ne . data in/data out (i/o 0 Ci/o 7 ) data is written to or read from the X20C05 through the i/o pins. the i/o pins are placed in the high impedance state when either ce or oe is high or when ne is low. write enable ( we ) the write enable input controls the writing of data to the ram. nonvolatile enable ( ne ) the nonvolatile enable input controls the recall function to the e 2 prom array. autostore output ( as ) as is an open drain output which, when asserted indi- cates v cc has fallen below the autostore threshold (v asth ). as may be wire-ored with multiple open drain outputs and used as an interrupt input to a microcontroller. v cc sense row select control logic column select & i/os eeprom array high speed 512 x 8 sram array ce oe we ne a 3 Ca 6 i/o 0 Ci/o 7 as a 0 Ca 2 a 7 Ca 8 recall store 3827 fhd f01 pin names symbol description a 0 Ca 8 address inputs i/o 0 Ci/o 7 data input/output we write enable ce chip enable oe output enable ne nonvolatile enable as autostore output v cc +5v v ss ground nc no connect 3827 pgm t01 functional diagram
X20C05 3 device operation the ce , oe , we and ne inputs control the X20C05 operation. the X20C05 byte-wide novram uses a 2-line control architecture to eliminate bus contention in a system environment. the i/o bus will be in a high impedance state when either oe or ce is high, or when ne is low. ram operations ram read and write operations are performed as they would be with any static ram. a read operation requires ce and oe to be low with we and ne high. a write operation requires ce and we to be low with ne high. there is no limit to the number of read or write operations performed to the ram portion of the X20C05. memory transfer operations there are two memory transfer operations: a recall operation whereby the data stored in the e 2 prom array is transferred to the ram array; and a store operation which causes the entire contents of the ram array to be stored in the e 2 prom array. recall operations are performed automatically upon power-up and under host system control when ne , oe and ce are low and we is high. the recall operation takes a maximum of 5 m s. there are two methods of initiating a store operation. the first is the software store command. this command takes the place of the hardware store employed on the x20c04. this command is issued by entering into the special command mode: ne , ce, and we strobe low while at the same time a specific address and data combination is sent to the device. this is a three step operation: the first address/data combination is 155[h]/aa[h]; the second combination is 0aa[h]/55[h]; and the final command combination is 155[h]/33[h]. this sequence of pseudo write operations will immedi- ately initiate a store operation. refer to the software command timing diagrams for details on set and hold times for the various signals. the second method of storing data is through the autostore command. when enabled, data is auto- matically stored from the ram into the e 2 prom array whenever v cc falls below the preset autostore threshold. this feature is enabled by performing the first two steps for the software store with the command combination being 155[h]/cc[h]. the autostore feature is disabled by issuing the three step command sequence with the command com- bination being 155[h]/cd[h]. the autostore feature will also be reset if v cc falls below the power-up reset threshold (approximately 3.5v) and is then raised back into the operating range. data protection the X20C05 supports two methods of protecting the nonvolatile data. if after power-up the autostore feature is not enabled, no autostore can occur. if after power-up no ram write operations have oc- curred no store operation can be initiated. the software store and autostore commands will be ignored. symbol table waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don? care: changes allowed changing: state not known n/a center line is high impedance
X20C05 4 d.c. operating characteristics (over recommended operating conditions unless otherwise specified.) limits symbol parameter min. max. units test conditions l cc1 v cc current (active) 100 ma ne = we = v ih , ce = oe = v il address inputs = 0.4v/2.4v levels @ f = 20mhz. all i/os = open i cc2 v cc current during store 5 ma all inputs = v ih i cc3 v cc current during 2.5 ma all i/os = open autostore i sb1 v cc standby current 10 ma ce = v ih (ttl input) all other inputs = v ih , all i/os = open i sb2 v cc standby current 250 m a all inputs = v cc C 0.3v (cmos input) all i/os = open i li input leakage current 10 m av in = v ss to v cc i lo output leakage current 10 m av out = v ss to v cc , ce = v ih v il (1) input low voltage C1 0.8 v v ih (1) input high voltage 2 v cc + 0.5 v v ol output low voltage 0.4 v i ol = 4ma v olas autostore output 0.4 v i olas = 1ma v oh output high voltage 2.4 v i oh = C4ma 3827 pgm t04.3 notes: (1) v il min. and v ih max. are for reference only and are not tested. (2) this parameter is periodically sampled and not 100% tested. absolute maximum ratings* temperature under bias .................. C65 c to +135 c storage temperature ....................... C65 c to +150 c voltage on any pin with respect to v ss ....................................... C1v to +7v d.c. output current ........................................... 10ma lead temperature (soldering, 10 seconds) ...... 300 c *comment stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. capacitance t a = +25 c, f = 1mhz, v cc = 5v. symbol test max. units conditions c i/o (2) input/output capacitance 10 pf v i/o = 0v c in (2) input capacitance 6 pf v in = 0v 3827 pgm t06.2 recommended operating conditions temperature min. max. commercial 0 c +70 c industrial C40 c +85 c military C55 c +125 c 3827 pgm t02.1 supply voltage limits X20C05 5v 10% 3827 pgm t03.1 power-up timing symbol parameter max. units t pur (2) power-up to ram operation 100 m s t puw (2) power-up to nonvolatile operation 5 ms 3827 pgm t05
X20C05 5 endurance and data retention parameter min. units endurance 100,000 data changes per bit store cycles 1,000,000 store cycles data retention 100 years 3827 pgm t07.1 mode selection ce we ne oe mode i/o power h x x x not selected output high z standby l h h l read ram output data active l l h h write 1 ram input data high active l l h h write 0 ram input data low active l h l l array recall output high z active l l l h software command input data active l h h h output disabled output high z active l l l l not allowed output high z active l h l h no operation output high z active 3827 pgm t09 a.c. conditions of test input pulse levels 0v to 3v input rise and fall times 5ns input and output timing levels 1.5v 3827 pgm t08.2 equivalent a.c. load circuit 5v 735 w 318 w output 30pf 3827 fhd f04
X20C05 6 a.c. characteristics (over the recommended operating conditions unless otherwise specified) read cycle limits X20C05-35 X20C05-45 X20C05-55 symbol parameter min. max. min. max. min. max. units t rc read cycle time 35 45 55 ns t ce chip enable access time 35 45 55 ns t aa address access time 35 45 55 ns t oe output enable access time 20 25 30 ns t lz (3) chip enable to output in low z 0 0 0 ns t olz (3) output enable to output in low z 0 0 0 ns t hz (3) chip disable to output in high z 15 20 25 ns t ohz (3) output disable to output in high z 15 20 25 ns t oh output hold from address change 0 0 0 ns 3827 pgm t10 read cycle 3827 fhd f05 note: (3) t lz min., t hz , t olz min., and t ohz are periodically sampled and not 100% tested. t hz and t ohz are measured, with c l = 5pf, from the point when ce or oe return high (whichever occurs first) to the time when the outptus are no longer driven. t ce t rc address ce oe we data valid data valid t oe t lz t olz t oh t aa t hz t ohz data i/o t oe v ih
X20C05 7 write cycle limits X20C05-25 X20C05-35 X20C05-45 X20C05-55 symbol parameter min. max. min. max. min. max. min. max. units t wc write cycle time 25 35 45 55 ns t cw chip enable to end of write input 25 30 35 40 ns t as address setup time 0 0 0 0 ns t wp write pulse width 30 30 35 40 ns t wr write recovery time 0 0 0 0 ns t dw data setup to end of write 15 15 20 25 ns t dh data hold time 0 0 3 3 ns t wz (4) write enable to output in high z 15 20 25 ns t ow (4) output active from end of write 5 5 5 5 ns t oz (4) output enable to output in high z 15 20 25 ns 3827 pgm t11 we controlled write cycle t wc t cw t as t oz t wp t dw t dh t ow t wr data valid address oe ce we data out data in 3827 fhd f06 note: (4) t wz , t ow and t oz are periodically sampled and not 100% tested.
X20C05 8 ce controlled write cycle 3827 fhd f07.1 t wc t cw t as t wp t dw t dh t wr data valid address oe ce we data out data in t wz t ow v ih
X20C05 9 array recall cycle limits X20C05-35 X20C05-45 X20C05-55 symbol parameter min. max. min. max. min. max. units t rcc array recall cycle time 5 5 5 m s t rcp (5) recall pulse width to 30 1000 40 1000 50 1000 ns initiate recall t rwe we setup time to ne 000ns 3827 pgm t13.1 array recall cycle address ne oe we ce data i/o t rcc t rcp t rwe 3827 fhd f10 note: (5) the recall pulse width (t rcp ) is a minimum time that ne , oe and ce must be low simultaneously to insure data integrity, ne and ce.
X20C05 10 software command timing limits X20C05-35 X20C05-45 X20C05-55 symbol parameter min. max. min. max. min. max. units t sto store cycle time 5 5 5 ms t sp (6) store pulse width 30 40 50 ns t sph store pulse hold time 35 45 55 ns t wc write cycle time 35 45 55 ns t as address setup time 0 0 0 ns t ah address hold time 0 0 0 ns t ds data setup time 15 20 25 ns t dh data hold time 0 3 3 ns t soe (7) oe disable to store function 20 20 20 ns t oest (7) output enable from end of store 10 10 10 ns t nhz (7) nonvolatile enable to output in 15 20 25 ns high z t nes ne setup time 5 5 5 ns t neh ne hold time 5 5 5 ns 3827 pgm t12.1 notes: (6) the store pulse width (t sp ) is a minimum time that ne , we and ce must be low simultaneously. (7) t soe , t oest and t nhz are periodically sampled and not 100% tested. ce controlled software command sequence 3827 fhd f08.2 cmd address 155 0aa 155 55 aa oe ce we ne data out data in t wc t as t sp t sph t ah t nhz t soe t dh t ds t sto t oest t neh t nes
X20C05 11 we controlled software command sequence 3827 fhd f09.2 cmd address 155 0aa 155 55 aa oe ce we ne data out data in t wc t sp t sph t ah t nhz t soe t dh t ds t sto t oest t as t nes t neh
X20C05 12 autostore feature the autostore feature automatically saves the con- tents of the X20C05s ram to the on-board bit-for-bit shadow e 2 prom at power-down. this circuitry insures that no data is lost during accidental power-downs or general system crashes, and is ideal for microprocessor caching systems, embedded software systems, and general system back-up memory. the autostore instruction (eas) to the sdp register sets the autostore enable latch, allowing the X20C05 to automatically perform a store operation whenever v cc falls below the autostore threshold (v asth ). v cc must remain above the autostore cycle end volt- age (v asend ) for the duration of the store cycle (t asto ). the detailed timing for this feature is illustrated in the autostore timing diagram, below. once the autostore cycle is initiated, all other device functions are inhibited. autostore cycle timing diagrams 3827 fhd f14 autostore cycle limits X20C05 symbol parameter min. max. units t asto autostore cycle time 2.5 ms v asth autostore threshold voltage 4.0 4.3 v v asend autostore cycle end voltage 3.5 v 3827 pgm t15 as t pur t asto t pur 0v v asth v cc 1 2 3 4 5 v cc volts (v) time (ms) v asth v asend autostore cycle in progress t asto store time
X20C05 13 sdp (software data protection) store state diagram software data protection commands command data eas enable autostore cc[h] ras reset autostore cd[h] ss software store 33[h] 3827 pgm t14.1 power up s0 s1 s2 store on ss or enable / reset autostore no store no store no store addr 155, data aa addr 155, data aa addr 155, data aa addr 0aa, data 55 write: addr 555, data=command ram write or recall 3827 fhd f12.1 power up software store enabled software store & autostore enabled power down eas ss ras power down (autostore) eas ss power on recall 3827 fhd f13.1
X20C05 14 0.620 (15.75) 0.590 (14.99) typ. 0.614 (15.60) 0.110 (2.79) 0.090 (2.29) typ. 0.100 (2.54) 1.30 (33.02) ref. 0.026 (0.66) 0.014 (0.36) typ. 0.018 (0.46) 0.225 (5.72) 0.140 (3.56) 0.060 (1.52) 0.015 (0.38) pin 1 seating plane 0.200 (5.08) 0.125 (3.18) 0.070 (1.78) 0.030 (0.76) typ. 0.055 (1.40) 0.610 (15.49) 0.500 (12.70) 0.100 (2.54) 0.035 (0.89) typ. 0.010 (0.25) 0 15 28-lead hermetic dual in-line package type d note: all dimensions in inches (in parentheses in millimeters) 1.490 (37.85) 1.435 (36.45) packaging information
X20C05 15 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.17) 0.610 (15.49) 0.590 (14.99) 0.110 (2.79) 0.090 (2.29) 1.460 (37.08) 1.400 (35.56) 1.300 (33.02) ref. pin 1 index 0.160 (4.06) 0.125 (3.17) 0.030 (0.76) 0.015 (0.38) pin 1 seating plane 0.062 (1.57) 0.050 (1.27) 0.550 (13.97) 0.510 (12.95) 0.085 (2.16) 0.040 (1.02) 0 15 28-lead plastic dual in-line package type p note: all dimensions in inches (in parentheses in millimeters) typ. 0.010 (0.25) packaging information
X20C05 16 0.150 (3.81) bsc 0.300 (7.62) bsc 0.458 (11.63) CC 0.458 (11.63) 0.442 (11.22) pin 1 0.400 (10.16) bsc 0.560 (14.22) 0.540 (13.71) 0.020 (0.51) x 45 ref. 0.095 (2.41) 0.075 (1.91) 0.022 (0.56) 0.006 (0.15) 0.055 (1.39) 0.045 (1.14) typ. (4) plcs. 0.040 (1.02) x 45 ref. typ. (3) plcs. 0.050 (1.27) bsc 0.028 (0.71) 0.022 (0.56) (32) plcs. 0.200 (5.08) bsc 0.015 (0.38) 0.003 (0.08) 0.558 (14.17) CC 0.088 (2.24) 0.050 (1.27) 0.120 (3.05) 0.060 (1.52) pin 1 index corder 1 32 32-pad ceramic leadless chip carrier package type e note: 1. all dimensions in inches (in parentheses in millimeters) 2. tolerance: 1% ntl 0.005 (0.127) packaging information
X20C05 17 0.021 (0.53) 0.013 (0.33) 0.420 (10.67) 0.050 (1.27) typ. typ. 0.017 (0.43) 0.045 (1.14) x 45 0.300 (7.62) ref. 0.453 (11.51) 0.447 (11.35) typ. 0.450 (11.43) 0.495 (12.57) 0.485 (12.32) typ. 0.490 (12.45) pin 1 0.400 (10.16) ref. 0.553 (14.05) 0.547 (13.89) typ. 0.550 (13.97) 0.595 (15.11) 0.585 (14.86) typ. 0.590 (14.99) 3 typ. 0.048 (1.22) 0.042 (1.07) 0.140 (3.56) 0.100 (2.45) typ. 0.136 (3.45) 0.095 (2.41) 0.060 (1.52) 0.015 (0.38) seating plane 0.004 lead co C planarity 32-lead plastic leaded chip carrier package type j notes: 1. all dimensions in inches (in parentheses in millimeters) 2. dimensions with no tolerance for reference only packaging information
X20C05 18 limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemnification provisions appearing in its terms of sale on ly. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. xicor, inc. makes no warranty of merchantability or fitness tor any purpose. xicor, inc. rese rves the right to discontinue production and change specifications and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no o ther circuits, patents, licenses are implied. us. patents xicor products are covered by one or more of the following u.s. patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874, 967; 4,883,976. foreign patents and additional patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the sy stem with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. xicors products are not authorized for use as critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) sup port or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reaso nably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its satety or effectiveness. ordering information access time C35 = 35ns C45 = 45ns C55 = 55ns temperature range blank = commercial = 0 c to +70 c i = industrial = C40 c to +85 c m = military = C55 c to +125 c package d = 28-lead cerdip p = 28 lead plastic dip e = 32-pad ceramic lcc j = 32-lead plcc device X20C05 x x -x

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